Hi,
I want a check the a block diagram for CCR1009 series
where can i find it..?

and I just check the Routerboard.com
but I can't find it..

can come one post
architecture diagram of 1009?

None is available yet but it isn't too hard to puzzle together.

SFP port : Direct CPU
SFP+ port : Direct CPU
Port 1-4: Switch with 1Gbps CPU uplink to CPU (Basically a 5 port switch chip with one port internally connected)
Port 5-8: Direct CPU

Did you need to know anything else? Looking at other CCR block diagram's and how the TileGX CPU is built and what kind of buses it has can also be helpful!

SFP port seems to be part of the switch group according to the wiki :

http://wiki.mikrotik.com/wiki/Switch_Chip_Features

"Shiro" hoped both sfp ports are directly connected to the cpu. The Tile should support this.

From Tilera's site:
"Integrated I/O features include up to 12 ports of 1Gb Ethernet and 2 ports of 10Gb Ethernet, along with multiple PCI Express controllers that can be configured as either root complex or endpoints. An assortment of USB, RS-232, I2C and GPIO ports further consolidate the system peripherals into the TILE-Gx9 System-on-Chip (SoC)."

UPS is delivering my CCR1009-8G-1S-1S+ today (Germany), can't wait to put that thing under load testing

[x@mx] /interface ethernet switch port> print
Flags: I - invalid
# NAME SWITCH VLAN-MODE VLAN-HEADER DEFAULT-VLAN-ID
0 ether1 switch1 disabled leave-as-is auto
1 ether2 switch1 disabled leave-as-is auto
2 ether3 switch1 disabled leave-as-is auto
3 ether4 switch1 disabled leave-as-is auto
4 switch1-cpu switch1 disabled leave-as-is auto

Hmmm... i am not sure about the 1 gig sfp port, maybe its connected to switchport and not configurable or the wiki is wrong and its directly connected to the cpu. Can someone from Microtik comment on this please?

My company already CCR1009-8G-1S-1S+ have one ready for test
I think start testing to next week..
I hope a good test

open & found 1 Phychip atheros ar8033-al1a

maby 5-8Port connection to Phy =>Tile09 ?