Just watching a couple of "The Network Berg"'s videos on YT. Very good. He's just made me aware of the block diagrams for each device on the hardware page online. This is the hAP ax2. Do I read this right that the wireless interfaces don't benefit from hardware switching? Not that I think this is a big problem as most traffic coming through wireless is destined for the internet and therefore has to go through the CPU-bound router and firewall. Just checking I understand the design correctly.

Yep, the HAP ax^2 is not hardware offloaded.

It is documented here: https://help.mikrotik.com/docs/display/ ... Offloading look for “IPQ-PPE”.

As they write in comment 6: “ Currently, HW offloaded bridge support for the IPQ-PPE switch chip is still a work in progress. We recommend using, the default, non-HW offloaded bridge (enabled RSTP).” So there is still hope

Thanks for that. After I posted, Network Berg covered the hAP ax3 and said it didn't really have hardware switching at all. I noticed that some block diagrams says "Switch chip" outside the SOC and some just say "Switch" inside the core. Infer the later isn't hardware. Specifically the Gigabit PHY in the hAP ax2 diagram doesn't say "switch" at all.

As far as I know, wireless interfaces don't have any sort of hardware offload support on any MikroTik device. Any wireless traffic always has to go through the CPU. This is probably true for most other WiFi-enabled routers, as this seems to be an internal SoC interoperability architecture thing rather than MikroTik's decision.

Specifically the Gigabit PHY in the hAP ax2 diagram doesn't say "switch" at all.

That's because the Gigabit PHY chip (QCA8075) is just that, a gigabit PHY chip. It doesn't implement switch functionality. It only handles the Ethernet physical layer stuff. Think auto mdix, link speed negotiation, etc. It then just passes relatively raw data along to the SoC (IPQ chip) and passes the data from it along to an ethernet port of SoCs choice.

The switching happens on the SoC. There seems to be some special circuitry inside the SoC for hardware switching between the five Ethernet ports. I can't tell you what standards the switch inside the SoC supports and how good it actually is without a datasheet (and Qualcomm is a b*tch about datasheets, so no datasheet for me, yay). And MikroTik documentation seems to be kinda vague on how well-supported the IPQ switch is in RouterOS. There are bridging test results on ax2's product page, though, if you want them. Spoiler alert: they're pretty good.